1. Technical Field
The present invention relates to data processing systems, and more particularly to apparatus for controlling data flow between an input/output bus and a general data processor bus.
2. Background Art
The basic input/output (I/O) problem is how to couple two different bus types, an input/output bus and a general data processor bus. On the I/O device side, different devices having a spectrum of data rates generated by different peripherals must be handled by the I/O bus. Some devices have the added problem of quiet periods followed by very busy periods with sharp transitions between the two. In the past this problem has been resolved by providing buffers.
An example of prior apparatus for controlling data flow between an input/output bus and a general data processor bus is the channel apparatus shown in the King, et al. patent, U.S. Pat. No. 3,550,133, granted to IBM on Dec. 22, 1970. In this IBM data channel, the central processing unit (CPU) initiates input/output operations by means of a start I/O instruction. This instruction addresses a particular channel and a particular I/O device. In response to this instruction, the channel fetches a channel address word (CAW) from a fixed location in main storage. The CAW contains the indirect address of the first channel command word (CCW) which is a control word specifying the type of command to be executed and the storage buffer area for data.
The channel program comprises a series of CCWs, which are utilized by the channel to direct the input/output operation. One CCW may control a block of information to be stored in a contiguous storage area. If several blocks of information are to be stored in the different areas, a list of CCWs is used, designating storage area blocks which are stored together by chaining the CCWs.
A drawback of this type of input/output control is that once a channel has been selected to perform a particular chaining operation, the channel is dedicated to that operation until it is completed. Therefore, the channel remains connected to the device even though there may be long latent periods between blocks of data specified by CCWs in the chain.
To overcome this drawback, a different approach was taken in the Clark, et al. U.S. Pat. No. 3,725,864, which was granted to IBM on Apr. 3, 1973. In the Clark, et al. patent, a plurality of channels are provided for scheduling and executing input/output programs. Each channel is capable of being logically connected to a device through a crosspoint switch. I/O tasks are then placed in a queue which is common to all of the channels. The channels then extract tasks from the queue and execute channel programs associated with the tasks. During latent periods of devices, channel programs corresponding to the device are queued to device queues. This enables the channel to go on to another task. When a device is at a point where its program can be resumed, any free channel which has access to the device will respond, reenter the program by extracting it from the device queue, and resume execution of the channel program.
An example of prior apparatus for buffering I/O data is the channel apparatus shown in the Capowski, et al. U.S. Pat. No. 3,699,530 granted to IBM on Oct. 17, 1972. In this apparatus, multiple dedicated buffers are provided for each channel to ensure that all channels have an individual receptacle for receiving data which cannot be made unavailable due to transfers by other channels. Prior resolution of requests from channels control the use of the bus from the channel independently of subsequent priority resolution for use of the main storage. Once a channel transfers its storage address and data into its assigned dedicated buffer, that buffer, based on the storage address contained within it, enters storage priority for the particular logical storage unit desired. In this manner, the single queue of channel requests is rearranged into four independent request queues based on logical storage addresses.
This approach has the advantage that it does smooth out input/output transfers, but at the expense of requiring dedicated resources which are expensive. In modern very large integrated (VLSI) technology, chip space is at a premium and pin connections are limited. It therefore becomes important to reduce the amount of buffering provided on the chip while still maintaining data throughput efficiency.
It is an object of the present invention to provide an input/output processor to handle transfers between a packet-oriented multiprocessor system bus and an input/output bus.